Clock Jitter

Sep 22, 20211 min read

Tektronix Innovation Forum 2021 Sessions with Steve Sandler

TDR Functionality for Power Integrity (30 mins) During this smart bar session, learn how to use TDR techniques to better understand power...

Sep 22, 20211 min read

Solving Power Integrity Test Challenges with Guest Speaker for Q&A Steve Sandler of Picotest

Learn how to use the MSO6 Oscilloscope to measure input filter stability, PSRR, impedance, step load, inductors with DC bias, TDR, EMI,...

Apr 7, 20161 min read

Troubleshooting Clock Jitter and Identifying PDN Sensitivities

Power distribution network (‘PDN’) noise is one of the most common issues in low power applications. Whether you are powering ADCs,...

Nov 14, 20131 min read

Troubleshooting Distributed Power Systems: The Switch (Part 6 of the ongoing series.)

With those measurement requirements as background, Sandler examines how switching frequency and duty cycle affect power supply stability...

Oct 23, 20121 min read

Clock Power Optimization Depends On Jitter Control

Clock-jitter performance has become a top priority among clock, analog-to-digital controller (ADC), and power-supply manufacturers. Why?...