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Speakers: Steve Sandler, Managing Director at Picotest, Benjamin Dannan, Chief Technologist at Signal Edge Solutions, Chris Loberg, Sr. Technical Marketing Manager at Tektronix, Heidi Barnes, Applications Engineer for PI & SI at Keysight Technologies, Jason Sekanina, µModule Business Dev’t & Product Apps at Analog Devices

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Datacenter, AI, and other Super Computing applications are growing exponentially.  This has exerted pressure in a number of areas.  We are seeing power domains exceeding 2,000 Amps in socket.  This puts pressure on the semiconductor companies to manufacture even higher density and higher efficiency power modules.  We are showing examples of these new power modules in our DesignCon paper, titled "Design, Simulation & Validation Challenges of a Scalable 2000 Amp Core Power Rail."  There are numerous other implications as well.  Target impedance levels are at or below 30uOhms, which is a challenge to measure, requiring new instrument interfaces.  Large signal dynamic current transients are not evident from impedance measurements and are even more challenging.  These power levels also put a strain on thermal designs of both the chip and the board, requiring electro-thermal simulation.  The near fields from the 2000Amp switching pollutes the nearby SI lines requiring system-level analysis, including PI/SI crosstalk and EMI.  And measuring the di/dt of the dynamic current also presents new challenges.  Yet another issue is the increasing number of, and speed, and therefore higher power, transceivers.  These transceiver requirements are also straining available test methodologies and in particular thermal design.  These impacts are apparent in the updates to the QSFP transceiver specifications.

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This distinguished panel was hand-selected to represent the engineers in the trenches.  They’ll each discuss how this exponential growth in high-power computing is affecting them, whether it is changes to workflow, the development of new processes and methodologies, the demand for instrument developments that include more detailed waveform analysis, or other implications.  It’s a great opportunity for the attendees to ask questions and learn about these impacts.  If they haven’t been subjected to these challenges, rest assured they will!!   

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Takeaways:

The audience will be presented with a new way to address power supply noise immunity concerns in high-performance transceiver testing. New water-cooled probe-based testing solution for high-speed signal integrity noise injection is presented. Testing of PSRR, PSMR, and PSNR applications are explored.

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Intended Audience:

• Basic knowledge of GaN design and thermal concerns in high-performance interconnect testing
• Power Supply testing and noise impacts on Signal Integrity concerns
• Basic understanding of transceiver test evaluation and analysis
• Basic knowledge of power supply noise performance testing including rejection ratio, noise rejection, and modulation ratio
• Basic concepts of PCIe, PAM-4 and 400G/800G

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