By Benjamin Dannan and Steven Sandler, Picotest.com
High speed Printed Circuit Board (PCB) design requires well designed Power Delivery Networks (PDN) to support today's FPGAs and custom mixed-signal ASICs. The PDN contains important impedance information that can tell a designer how a system will react to dynamic currents and the impact of PCB layout. Considering the PDN is the transmission line between the Voltage Regulator Module (VRM) and the load, it is then important to make the starting point for a good PDN design at the VRM.
Today VRMs need to supply power to multiple VDD cores to support FPGAs and/or custom ASICs using multi-gigabit ethernet, PCIe, and DDR memory interfaces. With that being said, vendor information for a VRM’s output impedance is not available and not always accurate when it is supplied. Further, measuring ultra-low impedance on multiple VRMs or multi-topology DC-DC regulators is a challenge for any design engineer....
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