Hi, I've been using this probe successfully with the 0402 head. I've been probing a DNI 0402 capacitor footprint, but after several measurement (with some down-force) the sharp pins are damaging my pads. I wondered if anyone had tried other probing structures? I was thinking of using 4 well-spaced PTHs in a 2-port config. I could also add a similar structure for GND calibration. - B

In lesson 7, it's stated that a GND isolator (transformer or solid state) isn't needed for HF measurements. Although I use a J2102B, I'd like to understand why. I've wondered about this since reading that coax pigtails used in a VDD-VSS measurement carry a good differential signal at HF, and it's not necessary to connect separate VDD and VSS cables to 2 scope channels for subtraction. My guess is that at sufficiently high frequency, the distributed L of the cable presents a sufficiently high reactance to create a Z0~=50ohms, which dominates the distributed R of the cable shield. That makes the drop across the R insignificant, thus attenuating the CM signal. Is that right?

I need to measure the Zpdn of a system, which is currently in the prototype stage. The load will be an SoC, which we don't have yet, so this system will have a custom prototype BGA substrate. Among other things, I'm prototyping the VRM which can source >100A. I want to measure its impedance across its operating range, so I need to create an equivalent load. For transients, a LoadSlammer should do the trick. For steady-state Zpdn measurements, I need a DC load. An nice solution would be to synchronise a BODE100 to LoadSlammer pulses, but AFAIK that's not possible (and the durations of the pulses may be too short). At such high currents, I can't use wires and external electronic loads, due to the DC drops and inductance. Heat will obviously be an issue, so power resistors in heatsinks look like an option (mounted on the PCB and switched by FETs). Placement and current-share then becomes an issue, and it's clear that these devices aren't designed to minimise parasitic L and C. I'm wondering if it would be better to build a load on the BGA substrate using FETs? I'm a novice in this area - is there an off-the-shelf, small-footprint, low-risk way to do this, which makes heat-removal easy? Or is there a better way, which I'm missing? Thanks in advance.

In lesson 7, Steve sets the output level of the BODE100 to +13dBm, which I believe is the max. This was done to maximise SNR. While I understand that this would minimise quantisation noise from a DDS, isn't it also common for an amplifier to incur worse non-linear distortion when driven at its max level, then at its mid-range level? Best regards, - Brendan

Hi, I read the excellent DesignCon paper ('Power Integrity for 32 Gb/s SERDES Transceivers', by PICOTEST, Xilinx & Keysight), referenced in Lesson 1. In this paper, the advantage of raising the switching frequency of a DCDC is explored. I've had recent experience of choosing the BW of a DCDC converter's control-loop, which begs the question: 'How can we confidently simulate, to choose the highest practical BW of a DCDC, which will be well-behaved in a given PCB layout?' I would like to simulate the whole post-layout system: PSU, PDN and PCB, but sims of PCB parasitics are generally seen to be in a different world to sims of PSUs. When the frequencies of interest really are distinct this is fine, but I believe the line is being blurred. I can import a synthesised SPICE model of a [PCB+Package+die] Sigrity extraction into an LTspice time-domain sim with a power-supply, but it's hard to find examples of such whole-system sims, which makes me wary of doing this. Another reason I'd like to run whole-system sims is that modern core-rail transients caused by state-changes in accelerators can be very harsh (tens of amps in a few ns). These can have low repetition rates that fall within DCDC converter loop-BWs. It would be great to simulate everything in one large SPICE sim: DCDC, Cbulk, PCB, PDN, package, package-PDN, die, with the step-loads applied across the Cdie terminals. This would allow inspection of voltage deviation where it matters: at the die, which would also reveal resonances within the package. As my employer builds its own SoCs, I believe I should be able to achieve this. My question is quite general - all opinions and advice are welcome: - Why is this not done more widely? Are sims like this just too complex to be done with confidence? - Full 3D extractions of entire boards into many GHz aren't practical, so what can be done to constrain the required complexity of the extraction? - There are many way in which this could go wrong. What can be done to make this work reliably? In order to build confidence in such sims, what steps should be taken in building prototypes, and making measurements & models? Best regards, - Brendan